asahi kasei [AKD4631-vn] 2005/01 - 1 - general description AKD4631-vn is an evaluation board fo r the ak4631vn, 16bit mono codec with mic/spk amplifier. the AKD4631-vn can evaluate a/d converter and d/a c onverter separately in addition to loopback mode (a/d d/a). AKD4631-vn also has the digital audio interf ace and can achieve the in terface with digital audio systems via opt-connector. ? ordering guide AKD4631-vn --- evaluation board for ak4631vn (cable for connecting with printer port of ibm-at, compatible pc and control software are packed with this. this cont rol software does not support windows nt.) function ? dit/dir with optical input/output ? bnc connector for an external clock input ? 10pin header for serial control mode 10pin header control data 10pin header gnd beep/min/mout ak4114 opt in opt out clock gen ak4631vn svdd avdd dsp dvdd mic-jack spk-jack aout mic 5v regulator 3.3v figure 1. AKD4631-vn block diagram * circuit diagram and pcb layout are attached at the end of this manual. ak4631-vn evaluation board rev.0 a kd4631- v n
asahi kasei [AKD4631-vn] 2005/01 - 2 - evaluation board manual ? operation sequence 1) set up the power supply lines. 1-1) when avdd, dvdd, svdd, and vcc are supplied from the regulator. (avdd, dvdd, svdd, and vcc jack should be open.). see ? other jumper pins set up (page 10)?. [reg] (red ) = 5v [avdd] (orange) = open : 3.3v is supplied to avdd of ak4631-vn from regulator. [dvdd] (orange) = open : 3.3v is supplied to dvdd of ak4631-vn from regulator. [svdd] (blue) = open : 3.3v is supplied to svdd of ak4631-vn from regulator. [vcc] (orenge) = open : 3.3v is supplied to logic block from regulator. [avss] (black) = 0v : for analog ground [agnd] (black) = 0v : for analog ground [dgnd] (black) = 0v : for logic ground 1-2) when avdd, dvdd, svdd, and vcc are not supplied from the regulator. (avdd, dvdd, svdd, and vcc jack should be junction.) see ? other jumper pins set up (page 10)?. [reg] (red) = ?reg? jack should be open. [avdd] (orange) = 2.6 3.6v : for avdd of ak4631-vn (typ. 3.3v) [dvdd] (orange) = 2.6 3.6v : for dvdd of ak4631-vn (typ. 3.3v) [svdd] (blue) = 2.6 5.25v : for svdd of ak4631-vn (typ. 3.3v, 5.0v) [vcc] (orenge) = 2.6 3.6v : for logic (typ. 3.3v) [avss] (black) = 0v : for analog ground [agnd] (black) = 0v : for analog ground [dgnd] (black) = 0v : for logic ground each supply line should be distributed from the power supply unit. avdd and dvdd must be same voltage level. 2) set up the evaluation mode, jumper pins and dip switches. (see the followings.) 3) power on. the ak4631vn and ak4114 should be reset once bringing sw1, 2 ?l? upon power-up. ? evaluation mode in case of ak4631vn evaluation using ak4114, it is necessary to correspond to audio interface format for ak4631vn and ak4114. about ak4631vn?s audio interface format, refer to datasheet of ak4631vn. about ak4114?s audio interface format, refer to table 2 in this manual. applicable evaluation mode (1) evaluation of loop-back mode (a/d d/a) : pll, master mode (default) (2) evaluation of loop-back mode (a/d d/a) : pll, slave mode (pll reference clock: mcki pin) (3) evaluation of loop-back mode (a/d d/a) : pll, slave mode (p ll reference clock: bick or fck pin) (4) evaluation of using dir of ak4114 (opt-connector) : ext, slave mode (5) evaluation of using dit of ak4114 (opt-connector) : ext, slave mode
asahi kasei [AKD4631-vn] 2005/01 - 3 - (1) evaluation of loop-back mode (a/d d/a) : pll, master mode (default) a) set up jumper pins of mcki clock ?mckpd bit? in the ak4631-vn should be set to ?0?. x?tal of 11.2896mhz, 12mhz, 12.288mhz, 13mhz, 24mhz or 27mhz can be set in x2. x?tal of 11.2896mhz (default) is set on the AKD4631-vn. set ?no.8 of sw3? to ?h?. when an external clock (11.2896mhz, 12mhz, 12.288mhz, 13mhz, 24mhz or 27mhz) through a rca connector (j8: ext/bick) is supplied, select ext on jp21 (mclk_sel) and short jp17 (xte). jp23 (ext1) and r26 should be properly selected in order to mu ch the output impedance of the clock generator. b) set up jumper pins of bick clock output frequency (16fs/32fs/64fs) of bick should be set by ?bcko1-0 bit? in the ak4631-vn. there is no necessity for set up jp19. c) set up jumper pins of fck clock d) set up jumper pins of data when the ak4631vn is evaluated by loop-back mode (a/d d/a), the jumper pins should be set to the following. jp17 xte mclk_sel jp21 jp18 mkfs 256fs 512fs 1024fs xtl dir ext mcko jp6 mcki jp22 fck_sel 2fs ext jp28 fck adc dir 1fs jp26 4631_sdti adc dac/loop jp30 sdti dir adc jp29 jp20 bick jp27 bick_inv thr inv dir adc bick thr inv bick_sel jp19 ext 16fs 32fs 64fs
asahi kasei [AKD4631-vn] 2005/01 - 4 - (2) evaluation of loop-back mode (a/d d/a) : pll, slave mode (pll reference clock: mcki pin) a) set up jumper pins of mcki clock ?mckpd bit? in the ak4631vn should be set to ?0?. x?tal of 11.2896mhz (default) is set on the AKD4631-vn. in this case, the ak4631vn corresponds to pll reference clock of 12.2896mhz. in this evaluation mode, the output clock from mcko-pin of the ak4631vn is supplied to a divider (u3: 74vhc4040), bick and fck clocks are generated by the divider. then ?mcko bit? in the ak4631vn should be set to ?1?. when an external clock through a rca connector (j8: ext/bick) is supplied, select ext on jp21 (mclk_sel) and shor t jp17 (xte). jp23 (ext1) and r26 should be properly selected in order to match the output impedance of the clock generator. b) set up jumper pins of bick clock c) set up jumper pins of fck clock d) set up jumper pins of data when the ak4631-vn is evaluated by loop-back mode (a/d d/a), the jumper pins should be set to the following. jp17 xte mclk_sel jp21 jp18 mkfs 256fs 512fs 1024fs xtl dir ext mcko jp6 mcki jp28 fck adc dir jp22 fck_sel 2fs ext 1fs jp26 4631_sdti adc dac/loop jp30 sdti dir adc jp29 jp20 bick jp27 bick_inv thr inv dir adc bick thr inv bick_sel jp19 ext 16fs 32fs 64fs
asahi kasei [AKD4631-vn] 2005/01 - 5 - (3) evaluation of loop-back mode (a/d d/a) : pll, slave mode (pll reference clock: bick or fck pin) a) set up jumper pins of mcki clock ?mckpd bit? in the ak4631vn should be set to ?1?. jp6 (mcki) should be open. b) set up jumper pins of bick clock when an external clock through a rca connector j8 (ext/bick) is supplied, select ext on jp19 (mclk_sel) and short jp17 (xte). jp23 (ext1) and r26 should be properly selected in order to match the output impedance of the clock generator. in this evaluation mode, the selected clock from jp21 (mclk_sel) is supplied to a divider (u3: 74vhc4040), bick and fck clocks are generated by the divider. input frequency of master clock is set up in turn ?256fs?, ?512fs?, ?1024fs? from left. and input frequency of bick is set up in turn ?16fs?, ?32fs?, ?64fs? from left. jp17 xte mclk_sel jp21 xtl dir ext jp29 jp20 bick jp27 bick_inv thr inv dir adc bick thr inv jp18 mkfs 256fs 512fs 1024fs mcko jp18 mkfs 256fs 512fs 1024fs mcko jp18 mkfs 256fs 512fs 1024fs mcko bick_sel jp19 ext 16fs 32fs 64fs bick_sel jp19 ext 16fs 32fs 64fs bick_sel jp19 ext 16fs 32fs 64fs
asahi kasei [AKD4631-vn] 2005/01 - 6 - c) set up jumper pins of fck clock when an external clock through a rca connector j9 (fck) is supplied, select ext on jp22 (fck_sel). jp24 (ext2) and r27 should be properly selected in order to match the output impedance of the clock generator. d) set up jumper pins of data when the ak4631vn is evaluated by loop-back mode (a/d d/a), the jumper pins should be set to the following. jp28 fck adc dir jp22 fck_sel 2fs ext 1fs jp26 4631_sdti adc dac/loop jp30 sdti dir adc
asahi kasei [AKD4631-vn] 2005/01 - 7 - (4) evaluation of using dir of ak4114 (opt-connector) : ext, slave mode a) set up jumper pins of mcki clock ?mckpd bit? in the ak4631vn should be set to ?0?. b) set up jumper pins of bick clock c) set up jumper pins of fck clock jp24 (ext2) and r27 should be properly selected in order to match the output impedance of the clock generator. d) set up jumper pins of data when d/a converter of the ak4631-vn is evaluated by us ing dir of ak4114, the jumper pins should be set to the following. jp17 xte mclk_sel jp21 xtl dir ext jp6 mcki jp18 mkfs 256fs 512fs 1024fs jp29 jp20 bick jp27 bick_inv thr inv dir adc bick thr inv bick_sel jp19 ext 16fs 32fs 64fs jp28 fck adc dir jp22 fck_sel 2fs ext 1fs jp26 4631_sdti adc dac/loop jp30 sdti dir adc
asahi kasei [AKD4631-vn] 2005/01 - 8 - (5) evaluation of using dit of ak4114 (opt-connector) : ext, slave mode a) set up jumper pins of mcki clock ?mckpd bit? in the ak4631-vn should be set to ?0?. b) set up jumper pins of bick clock c) set up jumper pins of fck clock jp24 (ext2) and r27 should be properly selected in order to match the output impedance of the clock generator. d) set up jumper pins of data when a/d converter of the ak4631-vn is evaluated by us ing dir of ak4114, the jumper pins should be set to the following. jp17 xte mclk_sel jp21 xtl dir ext jp6 mcki jp18 mkfs 256fs 512fs 1024fs jp28 fck adc dir jp22 fck_sel 2fs ext 1fs jp26 4631_sdti adc dac/loop jp30 sdti dir adc jp29 jp20 bick jp27 bick_inv thr inv dir adc bick thr inv bick_sel jp19 ext 16fs 32fs 64fs
asahi kasei [AKD4631-vn] 2005/01 - 9 - ? dip switch set up [sw3] (mode) : mode setting of ak4631-vn and ak4114 on is ?h?, off is ?l?. no. name on (?h?) off (?l?) 1 dif0 2 dif1 3 cm2 ak4114 audio format setting see table 2 4 cm0 5 cm1 clock operation mode select see table 3 6 ocks0 7 ocks1 master clock frequency select see table 4 8 m/s master mode slave mode note. when the ak4631-vn is evaluated master mode, ?no.8 of sw3? is set to ?h?. table 1. mode setting for ak4631-vn and ak4114 resistor setting for ak4631-vn audio interface format setting for ak4114 audio interface format dif1 bit dif0 bit dif0 dif1 dif2 daux sdto 0 1 l l l 24bit, left justified 16bit, right justified 1 0 l l h 24bit, left justified 24bit, left justified default 1 1 h l h 24bit, i 2 s 24bit, i 2 s note. when the ak4631-vn is evaluated by using dir/dit of ak4114, ?no.8 of sw3? is set to ?l?. table 2. setting for ak4114 audio interface format mode cm1 cm0 unlock pll x'tal clock source sdto 0 0 0 - on on(note) pll rx 1 0 1 - off on x'tal daux 0 on on pll rx 2 1 0 1 on on x'tal daux default 3 1 1 - on on x'tal daux on: oscillation (power-up), off: stop (power-down) note : when the x?tal is not used as clock comparison for fs detection (i.e. xtl1,0= ?1,1?), the x?tal is off. default setting is recommended. table 3. clock operation mode select no. ocks1 mcko1 mcko2 x?tal 0 0 256fs 256fs 256fs 2 1 512fs 256fs 512fs default table 4. master clock frequency select (stereo mode)
asahi kasei [AKD4631-vn] 2005/01 - 10 - ? other jumper pins set up 1. jp1 (gnd) : analog ground and digital ground open : separated. short : common. (the connector ?dgnd? can be open.) 2. jp2 (ain) : connection between micout pin and ain pin of the ak4631vn. open : no connection. short : connection. 3. jp3 (avdd_sel) : avdd of the ak4631vn reg : avdd is supplied from the regulator (?avdd? jack should be open). < default > avdd : avdd is supplied from ?avdd ? jack. 4. jp9 (dvdd_sel) : dvdd of the ak4631vn avdd : dvdd is supplied from ?avdd?. < default > dvdd : dvdd is supplied from ?dvdd ? jack. 5. jp10 (lvc_sel) : logic block of lvc is selected supply line. dvdd : logic block of lvc is supplied from ?dvdd?. < default > vcc : logic block of lvc is supplied from ?vcc ? jack. 6. jp11 (vcc_sel) : logic block is selected supply line. lvc : logic is supplied from supply line of lvc. < default > vcc : logic block of lvc is supplied from ?vcc ? jack. 7. jp4 (svdd_sel) : svdd of the ak4631vn reg : svdd is supplied from the regul ator (?svdd? jack should be open). < default > svdd : svdd is supplied from ?svdd ? jack. 8. jp8 (mcko_sel) : master clock frequency is selected clock from mcko1 or mcko2 of the ak4114. mcko1 : the check from mcko1 of ak4114 is provided to mcki of the ak4631vn. < default > mcko2 : the check from mcko2 of ak4114 is provided to mcki of the ak4631vn.
asahi kasei [AKD4631-vn] 2005/01 - 11 - ? the function of the toggle sw [sw1] (dir) : power control of ak4114. keep ?h? during normal operation. keep ?l? when ak4114 is not used. [sw2] (pdn) : power control of ak4631vn. keep ?h? during normal operation. ? indication for led [led1] (erf): monitor int0 pin of the ak4114. led turns on when some error has occurred to ak4114. ? serial control the ak4631-vn can be controlled via the printer port (parallel port) of ibm-at compatible pc. connect port2 (ctrl) with pc by 10 wire flat cable packed with the AKD4631-vn connect csn cclk cdti 10pin header 10pin connector 10 wire flat cable pc AKD4631-vn figure 2. connect of 10 wire flat cable
asahi kasei [AKD4631-vn] 2005/01 - 12 - ? analog input / output circuits (1) input circuits a) mic input circuit figure 3. mic input circuit (a-1) analog signal is input to mic pin via j1 connector. jp12 mic_sel jack rca (a-2) analog signal is input to mic pin via j3 connector. jp12 mic_sel jack rca j3 mr-552ls avss avss jack 1 jp12 mic_ sel int mic 3 rca j1 mic- ja ck 6 4 3 2
asahi kasei [AKD4631-vn] 2005/01 - 13 - (2) output circuits a) aout output circuit figure 4. aout output circuit j5 mr-552ls aout r20 220 2 1 3 r21 20k + c28 1u 1 2 avss avss aout
asahi kasei [AKD4631-vn] 2005/01 - 14 - b) spk output circuit note. when mini-jack is inserted or pulled out j2 (spk-jack) connector, jp13 (spp_sel) and jp14 (spn_sel) should be open, or ?pmspk bit? in the ak4631-vn should be set to ?0?. figure 5. spk output circuit (b-1) an external dynamic speaker is evaluated by using j2 (spk-jack) connector. (b-2) an external piezo speaker is evaluated by using j2 (spk-jack) connector. spp jp13 spp_ sel spk1 dynamic d2 diode z ener a k jp14 spn_sel piezo(ext) dynamic(ext) 020s16 svss r r15 10 piezo(ext) l r17 10 d1 diode z ener a k jp31 dynamic cn5 1 2 dynamic svss j2 spk-jack 6 4 3 dynamic(ext) spn svss jp14 spn_sel dynamic dynamic(ext) piezo(ext) jp13 spp_sel dynamic dynamic(ext) piezo(ext) jp31 dynamic jp14 spn_sel dynamic dynamic(ext) piezo(ext) jp13 spp_sel dynamic dynamic(ext) piezo(ext) jp31 dynamic
asahi kasei [AKD4631-vn] 2005/01 - 15 - (b-3) analog signal of spp/spn pins are output from ?dynamic speaker? on the evaluation (spk1). (3) beep/min/mout input and output circuit figure 6. beep/min/mout input and output circuit (3-1) analog signal is input to min pin from j4 connector. jp15 min/mout out in jp16 beep/min/mout mout min beep (3-2) analog signal of mout pin is output from j4 connector. jp15 min/mout out in jp16 beep/min/mout mout min beep jp14 spn_sel dynamic dynamic(ext) piezo(ext) jp13 spp_sel dynamic dynamic(ext) piezo(ext) jp31 dynamic j4 mr-552ls beep/ min/ mout + c24 1u 1 2 min r18 47k out r16 20k jp16 beep/ min/ mout in beep beep jp15 min/ mout min mout avss + c26 1u 1 2 r19 20k 1 avss 3 avss c25 0.1u mout 2
asahi kasei [AKD4631-vn] 2005/01 - 16 - (3-3) analog signal of mout pin is input to min pin. jp15 min/mout out in jp16 beep/min/mout mout min beep (3-4) analog signal is input to beep pin from j4 connector. jp15 min/mout out in jp16 beep/min/mout mout min beep ? akm assumes no responsibility for the trouble when using the above circuit examples.
asahi kasei [AKD4631-vn] 2005/01 - 17 - control software manual ? set-up of evaluation board and control software 1. set up the AKD4631-vn according to previous term. 2. connect ibm-at compatible pc with AKD4631vn by 10-line type flat cable (packed with AKD4631-vn). take care of the direction of 10pin header. (please install the driver in the cd-rom when this control software is used on windows 2000/xp. please refer ?installation manual of control software driver by akm device control software?. in case of windows95/98/me, this installation is not n eeded. this control software does not operate on windows nt.) 3. insert the cd-rom labeled ?ak4631vn evaluation kit? into the cd-rom drive. 4. access the cd-rom drive and double-click the icon of ?AKD4631.exe? to set up the control program. 5. then please evaluate according to the follows. ? operation flow keep the following flow. 1. set up the control program according to explanation above. 2. click ?write default? button. 3. then set up the dialog and input data. ? explanation of each buttons 1. [port setup] : set up the printer port. 2. [write default] : initialize the register of ak4631-vn. 3. [all write] : write all registers that is currently displayed. 4. [function1] : dialog to write data by keyboard operation. 5. [function2] : dialog to write data by keyboard operation. 6. [f3] : dialog of sequential writing. 7. [save] : save the current register setting. 8. [open] : write the saved values to all register. 9. [write] : dialog to write data by mouse operation.
asahi kasei [AKD4631-vn] 2005/01 - 18 - ? explanation of each dialog 1. [function1 dialog] : dialog to write data by keyboard operation address box: input registers address in 2 figures of hexadecimal. data box: input registers data in 2 figures of hexadecimal. if you want to write the input data to ak4631vn, click ?ok? button. if not, click ?cancel? button. 2. [function2 dialog] : dialog to evaluate ivol address box: input registers address in 2 figures of hexadecimal. start data box: input starts data in 2 figures of hexadecimal. end data box: input end data in 2 figures of hexadecimal. interval box: data is writte n to ak4631vn by this interval. step box: data changes by this step. mode select box: if you check this check box, data reaches end data, and returns to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 if you do not check this check box, data reaches end data, but does not re turn to start data. [example] start data = 00, end data = 09 data flow: 00 01 02 03 04 05 06 07 08 09 if you want to write the input data to ak4631vn, click ?ok? button. if not, click ?cancel? button. 3. [write dialog] : dialog to write data by mouse operation there are dialogs corres ponding to each register. click the ?write? button corresponding to each register to set up the dialog. if you check the check box, data becomes ?h? or ?1?. if not, ?l? or ?0?. if you want to write the input data to ak4631vn, click ?ok? button. if not, click ?cancel? button.
asahi kasei [AKD4631-vn] 2005/01 - 19 - ? indication of data input data is indicated on the register map. red letter indicates ?h? or ?1? and blue one indicates ?l? or ?0?. blank is the part that is not defined in the datasheet. ? attention on the operation if you set up function1 or function2 dialog, input data to all boxes. attention dialog is indicated if you input data or address that is not specified in the datasheet or you clic k ?ok? button before you input data. in that case set up the dialog and input data once more again. these operations does not need if you click ?cancel? button or check the check box.
asahi kasei [AKD4631-vn] 2005/01 - 20 - 1.ak4631 mode: ext mode (slave) [measurement condition] ? measurement unit: rohde & schwarz, upd05 ? mcki: 256fs, 512fs ? bick: 64fs ? bit: 16bit ? sampling frequency: 8khz & 16khz ? measurement frequency: 20 3.4khz (fs=8khz), 20 8khz (fs=16khz) ? power supply: avdd=dvdd=3.3v,svdd=3.3v/5.0v ? temperature: room ? input frequency: 1khz [measurement results] 1.adc characteristics (mic gain = +20db, ipga=0db, alc1 = off, mic ? ipga ? adc) result mcki clock 512fs 256fs sampling frequency 8khz 16khz 8khz 16khz s/(n+d) (-1dbfs) 84.6db 84.1db 85.2db 84.1db d-range (-60dbfs) 86.1db 85.0db 88.6db 84.9db s/n 86.1db 85.0db 88.6db 85.0db 2. dac characteristics (aout) (dac ? aout, dvol = 0db) result mcki clock 512fs 256fs sampling frequency 8khz 16khz 8khz 16khz s/(n+d) (0dbfs) 89.7db 89.0db 86.0db 91.9db d-range (-60dbfs) 93.5db 91.1db 93.7db 95.3db s/n 94.1db 92.2db 94.5db 95.3db 3. speaker-amp characteristics (dac mout min ? spp/spn, alc2=off) result spkg1-0 = ?00? (-0.5dbfs) 65.8db svdd=3.3v rl=8
spkg1-0 = ?01? (-0.5dbfs) 67.8db spkg1-0 = ?10? (-0.5dbfs) 74.5db s/(n+d) svdd=5.0v rl=50
spkg1-0 = ?11? (-0.5dbfs) 78.1db spkg1-0 = ?00? 90.2db svdd=3.3v rl=8
spkg1-0 = ?01? 90.4db spkg1-0 = ?10? 90.3db s/n svdd=5.0v rl=50
spkg1-0 = ?11? 90.4db 4. loop-back (mic ? adc ? dac ? aout) result mcki clock 512fs 256fs sampling frequency 8khz 16khz 8khz 16khz s/(n+d) (-1dbfs) 84.4db 84.0db 84.7db 84.0db d-range (-60dbfs) 85.9db 84.8db 87.8db 84.5db s/n 86.0db 84.8db 87.9db 84.6db measurement results example
asahi kasei [AKD4631-vn] 2005/01 - 21 - 2.ak4631 mode: pll slave mode [measurement condition] ? measurement unit: rohde & schwarz, upd05 ? bit: 16bit ? sampling frequency: 8khz & 16khz ? measurement frequency: 20 3.4khz (fs=8khz), 20 8khz (fs=16khz) ? power supply: avdd=dvdd=svdd=3.3v ? temperature: room ? input frequency: 1khz [measurement results] 2-1. pll reference clock : bick or fck pin loop-back (mic ? adc ? dac ? aout) result pll reference clock 1fs (fck pin) 16fs (bick pin) sampling frequency 8khz 16khz 8khz 16khz s/(n+d) (-1dbfs) 65.1db 72.2db 85.0db 83.6db d-range (-60dbfs) 86.3db 85.0db 87.8db 85.0db s/n 86.4db 85.0db 87.9db 85.0db 2-2. pll reference clock : mcki pin loop-back (mic ? adc ? dac ? aout) result pll reference clock 12.288mhz sampling frequency 8khz 16khz s/(n+d) (-1dbfs) 84.5db 83.4db d-range (-60dbfs) 86.3db 85.1db s/n 86.6db 85.2db 3.ak4631 mode: pll master mode [measurement condition] ? measurement unit: rohde & schwarz, upd05 ? mcki: 12.288 mhz ? bick: 16fs ? bit: 16bit ? sampling frequency: 8khz & 16khz ? measurement frequency: 20 3.4khz (fs=8khz), 20 8khz (fs=16khz) ? power supply: avdd=dvdd=svdd=3.3v ? temperature: room ? input frequency:1khz [measurement results] loop-back (mic ? adc ? dac ? aout) result 8khz 16khz s/(n+d) (-1dbfs) 84.4db 83.9db d-range (-60dbfs) 86.1db 85.3db s/n 86.4db 85.3db
asahi kasei [AKD4631-vn] 2005/01 - 22 - 4.plot data (ext slave mode) 4-1.adc (mic ? adc) plot data figure 8. thd+n vs. input level figure 9. thd+n vs. input frequency (input level = -1dbfs)
asahi kasei [AKD4631-vn] 2005/01 - 23 - figure 10. linearity figure 11. frequency response
asahi kasei [AKD4631-vn] 2005/01 - 24 - figure 12. fft plot ( input level=-1.0dbfs) figure 13. fft plot ( input level=-60.0dbfs )
asahi kasei [AKD4631-vn] 2005/01 - 25 - figure 14. fft plot ( ?0? data input )
asahi kasei [AKD4631-vn] 2005/01 - 26 - 4-2. dac (dac ? aout) plot data figure 15. thd+n vs. input level figure 16. thd+n vs. input frequency (input level = 0dbfs)
asahi kasei [AKD4631-vn] 2005/01 - 27 - figure 17. linearity figure 18. frequency response
asahi kasei [AKD4631-vn] 2005/01 - 28 - figure 19. fft plot ( input level=0dbfs ) figure 20. fft plot ( input level=-60.0dbfs )
asahi kasei [AKD4631-vn] 2005/01 - 29 - figure 21. fft plot ( ?0? data input )
asahi kasei [AKD4631-vn] 2005/01 - 30 - revision history date manual revision board revision reason contents 04/01/25 km077300 0 first edition important notice ? these products and their specific ations are subject to change with out notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concer ning their current status. ? akm assumes no liability for infringement of any pa tent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or syst ems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system , and akm assumes no responsibility relating to any such use, except with the express written cons ent of the representative director of akm. as used here: (a) a hazard related device or system is one design ed or intended for life support or maintenance of safety or for applications in medicine, aerospace , nuclear energy, or other fields, in which its failure to function or perform may reasonably be expect ed to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to f unction or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore me et very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.
a a b b c c d d e e e e d d c c b b a a svdd reg_in avdd dvdd vcc(3.3v) reg_in avdd dvdd svdd 4631_mcki int mout 4631_sdto spn beep spp cclk 4631_fck aout min avdd 4631_bick dvdd cdti reg reg reg 4631_mcko pdn csn 4631_sdti avdd dvdd lvc d3.3v title size document number rev date: sheet of ak4631-vn 0 AKD4631-vn a3 15 wednesday, december 22, 2004 title size document number rev date: sheet of ak4631-vn 0 AKD4631-vn a3 15 wednesday, december 22, 2004 title size document number rev date: sheet of ak4631-vn 0 AKD4631-vn a3 15 wednesday, december 22, 2004 reg svdd reg avdd avss svss avss avss svss dvdd avss avdd avss avss avss svss vcc dvdd lvc vcc avss svss avss avss avss svss 1 tp22 svdd tp22 svdd c8 4.7n c8 4.7n jp6 mcki jp6 mcki c7 0.22u c7 0.22u in out gnd t1 ta48033f t1 ta48033f 1 tp29 micout tp29 micout + c21 10u + c21 10u + c12 10u + c12 10u 1 tp3 avss tp3 avss 1 tp13 sdto tp13 sdto 1 tp23 svss tp23 svss r8 51 r8 51 r40 (short) r40 (short) 1 2 + c22 47u + c22 47u 1 2 l2 (short) l2 (short) 1 tp18 mcki tp18 mcki jp9 dvdd_sel jp9 dvdd_sel 25 26 27 28 29 30 31 32 cn1 32pin_4 cn1 32pin_4 1 tp25 mout tp25 mout r14 10 r14 10 jp1 gnd jp1 gnd r13 470 r13 470 1 tp14 fck tp14 fck 1 tp2 avdd tp2 avdd c10 0.1u c10 0.1u r11 51 r11 51 r6 51 r6 51 jp2 ain jp2 ain 1 tp9 csn tp9 csn 1 svss t45_bk svss t45_bk 1 tp24 min tp24 min c2 0.1u c2 0.1u jp4 svdd_sel jp4 svdd_sel 9 10 11 12 13 14 15 16 cn4 32pin_2 cn4 32pin_2 r12 470 r12 470 c5 0.1u c5 0.1u r4 (open) r4 (open) 1 tp19 mcko tp19 mcko 1 tp1 vcoc tp1 vcoc 1 tp26 aout tp26 aout + c6 1u + c6 1u 1 tp10 cclk tp10 cclk 1 tp15 bick tp15 bick 1 2 + c23 47u + c23 47u 1 reg t45_r reg t45_r 1 svdd t45_bu svdd t45_bu jp10 lvc_sel jp10 lvc_sel r9 51 r9 51 1 tp30 mic tp30 mic 1 tp21 spp tp21 spp 1 2 3 4 5 6 7 8 cn2 32pin_1 cn2 32pin_1 r7 51 r7 51 1 2 l5 (short) l5 (short) r1 2.2k r1 2.2k 1 tp8 pdn tp8 pdn c1 0.1u c1 0.1u 1 2 l4 (short) l4 (short) + c9 10u + c9 10u 1 tp16 dvdd tp16 dvdd 1 tp27 beep tp27 beep 1 tp11 cdti tp11 cdti 1 avss t45_bk avss t45_bk c11 0.1u c11 0.1u 1 dvdd t45_o dvdd t45_o 1 tp31 mpi tp31 mpi 17 18 19 20 21 22 23 24 cn3 32pin_3 cn3 32pin_3 1 2 + c3 47u + c3 47u vcom 1 avss 2 avdd 3 vcoc 4 pdn 5 csn 6 cclk 7 cdti 8 sdti 9 sdto 10 fck 11 bick 12 dvdd 13 dvss 14 mcki 15 mcko 16 spp 17 spn 18 svdd 19 svss 20 min 21 mout 22 aout 23 beep 24 ain 25 micout 26 mic 27 mpi 28 u1 ak4631vn u1 ak4631vn 1 2 + c13 47u + c13 47u 1 2 l1 (short) l1 (short) r3 (short) r3 (short) 1 2 + c16 47u + c16 47u + c4 2.2u + c4 2.2u 1 tp28 ain tp28 ain 1 tp20 spn tp20 spn r2 10k r2 10k 1 tp12 sdti tp12 sdti jp3 avdd_sel jp3 avdd_sel jp11 vcc_sel jp11 vcc_sel 1 dgnd t45_bk dgnd t45_bk 1 tp32 vcom tp32 vcom 1 avdd t45_o avdd t45_o c20 0.1u c20 0.1u r10 51 r10 51 r5 (short) r5 (short)
a a b b c c d d e e e e d d c c b b a a mout spp spn int aout min beep title size document number rev date: sheet of input/output 0 AKD4631-vn a3 25 wednesday, december 22, 2004 title size document number rev date: sheet of input/output 0 AKD4631-vn a3 25 wednesday, december 22, 2004 title size document number rev date: sheet of input/output 0 AKD4631-vn a3 25 wednesday, december 22, 2004 in out jack avss avss avss avss avss avss 2 3 mic 1 rca beep/min/mout 2 3 1 avss mout min beep l r 020s16 spk1 svss dynamic(ext) dynamic piezo(ext) svss dynamic(ext) piezo(ext) dynamic 3 1 2 aout svss jp15 min/mout jp15 min/mout jp12 mic_sel jp12 mic_sel r18 47k r18 47k r21 20k r21 20k j3 mr-552ls j3 mr-552ls 1 2 + c26 1u + c26 1u j4 mr-552ls j4 mr-552ls r15 10 r15 10 jp16 beep/min/mout jp16 beep/min/mout a k d1 diode zener d1 diode zener r20 220 r20 220 c25 0.1u c25 0.1u jp13 spn_sel jp13 spn_sel r17 10 r17 10 6 4 3 j2 spk-jack j2 spk-jack r19 20k r19 20k jp31 dynamic jp31 dynamic 1 2 + c24 1u + c24 1u j5 mr-552ls j5 mr-552ls jp14 spp_sel jp14 spp_sel 6 4 3 j1 mic-jack j1 mic-jack r16 20k r16 20k a k d2 diode zener d2 diode zener 1 2 cn5 cn5 1 2 + c28 1u + c28 1u
a a b b c c d d e e e e d d c c b b a a vcc vcc ext_mclk ext_bick mcko dir_mclk ext_fck d3.3v title size document number rev date: sheet of clock 0 AKD4631-vn a3 35 wednesday, december 22, 2004 title size document number rev date: sheet of clock 0 AKD4631-vn a3 35 wednesday, december 22, 2004 title size document number rev date: sheet of clock 0 AKD4631-vn a3 35 wednesday, december 22, 2004 ext 1024fs 64fs 512fs 256fs 32fs inv thr 16fs 1fs xtl ext ext for 74hcu04,74ac74,74vhc4040,74hc14,74hc14,74hc541,74hct04 mcko dir 3 1 ext/bick avss 2 2 fck 1 3 avss 2fs d 2 clk 3 q 5 q 6 pr 4 cl 1 u4a 74ac74 u4a 74ac74 jp18 mkfs jp18 mkfs c33 0.1u c33 0.1u r26 51 r26 51 r27 51 r27 51 c34 0.1u c34 0.1u jp22 fck_sel jp22 fck_sel j8 mr-552ls j8 mr-552ls r25 short r25 short 1 2 u5a 74hc14 u5a 74hc14 r24 1m r24 1m 1 2 u2a 74hcu04 u2a 74hcu04 1 2 x1 12.288mhz x1 12.288mhz 3 4 u2b 74hcu04 u2b 74hcu04 d 12 clk 11 q 9 q 8 pr 10 cl 13 u4b 74ac74 u4b 74ac74 c36 0.1u c36 0.1u jp17 xte jp17 xte c35 0.1u c35 0.1u c31 0.1u c31 0.1u j9 mr-552ls j9 mr-552ls 1 2 + c37 47u + c37 47u jp23 ext1 jp23 ext1 c39 5p c39 5p clk 10 rst 11 q1 9 q2 7 q3 6 q4 5 q5 3 q6 2 q7 4 q8 13 q9 12 q10 14 q11 15 q12 1 u3 74vhc4040 u3 74vhc4040 c30 0.1u c30 0.1u c38 5p c38 5p jp20 bick jp20 bick c32 0.1u c32 0.1u jp24 ext2 jp24 ext2 jp19 bick_sel jp19 bick_sel jp21 mclk_sel jp21 mclk_sel
a a b b c c d d e e e e d d c c b b a a daux dir_sdti dir_bick dir_fck cm0 cm0 d3.3v d3.3v cm1 ocks0 cm1 ocks1 d3.3v d3.3v m/s d3.3v d3.3v d3.3v ocks1 ocks0 dir_mclk title size document number rev date: sheet of dir/dit 0 AKD4631-vn a3 45 wednesday, december 22, 2004 title size document number rev date: sheet of dir/dit 0 AKD4631-vn a3 45 wednesday, december 22, 2004 title size document number rev date: sheet of dir/dit 0 AKD4631-vn a3 45 wednesday, december 22, 2004 h l dif0 dif2 cm0 ocks1 m/s cm1 dif1 ocks0 mcko2 mcko1 1 2 + c43 10u + c43 10u c41 0.1u c41 0.1u c46 0.47u c46 0.47u ips0 1 nc 2 dif0 3 test2 4 dif1 5 nc 6 dif2 7 ips1 8 p/sn 9 xtl0 10 xtl1 11 tvdd 13 dvss 14 tx0 15 tx1 16 bout 17 cout 18 uout 19 vout 20 dvdd 21 dvss 22 mcko1 23 bick 26 mcko2 27 daux 28 xto 29 xti 30 pdn 31 cm0 32 cm1 33 ocks1 34 ocks0 35 int0 36 avdd 38 r 39 vcom 40 avss 41 rx0 42 nc 43 rx1 44 test1 45 rx2 46 nc 47 rx3 48 vin 12 lrck 24 sdto 25 int1 37 u6 ak4114 u6 ak4114 c44 0.1u c44 0.1u 1 2 + c51 10u + c51 10u 5 6 u5c 74hc14 u5c 74hc14 k a d3 hsu119 d3 hsu119 c49 0.1u c49 0.1u c53 0.1u c53 0.1u c48 5p c48 5p 1 2 + c52 10u + c52 10u 1 2 u7a 74hc04 u7a 74hc04 c50 0.1u c50 0.1u c47 5p c47 5p c45 0.1u c45 0.1u 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 sw3 sw3 r31 1k r31 1k 3 4 u5b 74hc14 u5b 74hc14 r29 470 r29 470 1 2 x2 11.2896mhz x2 11.2896mhz c42 0.1u c42 0.1u k a led1 erf led1 erf r30 18k r30 18k r28 10k r28 10k jp25 mcko_sel jp25 mcko_sel c40 0.1u c40 0.1u 2 1 3 sw1 dir sw1 dir gnd 1 vcc 2 in 3 port2 totx141 port2 totx141 out 1 vcc 3 gnd 2 port1 torx141 port1 torx141 1 2 l6 (short) l6 (short) 1 2 3 4 5 6 7 8 9 rp1 47k rp1 47k
a a b b c c d d e e e e d d c c b b a a 4631_sdti 4631_mcki daux 4631_fck 4631_bick lvc daux ext_bick dir_sdti 4631_mcki dir_fck ext_fck 4631_mcko m/s mcko 4631_sdto ext_mclk dir_bick d3v lvc d3v d3v csn cclk cdti pdn title size document number rev date: sheet of logic 0 AKD4631-vn a3 55 wednesday, december 22, 2004 title size document number rev date: sheet of logic 0 AKD4631-vn a3 55 wednesday, december 22, 2004 title size document number rev date: sheet of logic 0 AKD4631-vn a3 55 wednesday, december 22, 2004 fck adc adc dir mclk vcc sdti dir bick cclk cdti csn lh adc dir inv thr dac/loop adc jp27 bick jp27 bick jp26 4631_sdti jp26 4631_sdti 6 5 4 3 2 1 7 rp3 47k rp3 47k c57 0.1u c57 0.1u 1 2 3 4 5 6 7 8 9 10 port4 ctrl port4 ctrl 13 12 u10f 74hc14 u10f 74hc14 c55 0.1u c55 0.1u r38 10k r38 10k a1 2 y1 18 a2 3 y2 17 a3 4 y3 16 a4 5 y4 15 a5 6 y5 14 a6 7 y6 13 a7 8 y7 12 a8 9 y8 11 g1 1 g2 19 u11 74hc541 u11 74hc541 r37 470 r37 470 11 10 u10e 74hc14 u10e 74hc14 1 2 3 4 5 6 7 8 9 10 port3 rom port3 rom 2 1 3 sw2 pdn sw2 pdn 9 8 u5d 74hc14 u5d 74hc14 9 8 u10d 74hc14 u10d 74hc14 r32 10k r32 10k r35 470 r35 470 6 5 4 3 2 1 7 rp2 47k rp2 47k 13 12 u2f 74hcu04 u2f 74hcu04 13 12 u7f 74hc04 u7f 74hc04 r34 10k r34 10k 5 6 u10c 74hc14 u10c 74hc14 11 10 u2e 74hcu04 u2e 74hcu04 a1 2 a2 3 a3 4 a4 5 a5 6 a6 7 a7 8 a8 9 g1 1 g2 19 y1 18 y2 17 y3 16 y4 15 y5 14 y6 13 y7 12 y8 11 vcc 20 gnd 10 u9 74lvc541 u9 74lvc541 1 2 u10a 74hc14 u10a 74hc14 r39 10k r39 10k r36 10k r36 10k jp28 fck jp28 fck c54 0.1u c54 0.1u 11 10 u7e 74hc04 u7e 74hc04 k a d4 hsu119 d4 hsu119 jp29 bick_inv jp29 bick_inv r33 470 r33 470 9 8 u2d 74hcu04 u2d 74hcu04 1 2 + c56 47u + c56 47u 5 6 u2c 74hcu04 u2c 74hcu04 9 8 u7d 74hc04 u7d 74hc04 11 10 u5e 74hc14 u5e 74hc14 a1 2 a2 3 a4 5 a5 6 a6 7 a7 8 a8 9 dir 1 g 19 b1 18 b2 17 b3 16 b4 15 b5 14 b6 13 b7 12 b8 11 vcc 20 gnd 10 a3 4 u8 74lvc245 u8 74lvc245 3 4 u10b 74hc14 u10b 74hc14 5 6 u7c 74hc04 u7c 74hc04 jp30 sdti jp30 sdti 3 4 u7b 74hc04 u7b 74hc04
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